Dr. Anirudh Devgan is President and CEO of Cadence and is a member of the Board of Directors. Prior to becoming CEO in 2021, he was President of Cadence, before which he served as Executive Vice President and General Manager of the Digital & Signoff and System Verification groups. Prior to joining Cadence in 2012, Dr. Devgan was Corporate VP and member of the executive staff at Magma Design Automation and earlier held management and technical roles at IBM.

Dr. Devgan is widely recognized as one of the leading authorities in electronic design automation (EDA) and successfully pioneered the application of massively parallel and distributed architectures to create several industry firsts and most impactful products in the areas of SPICE simulation, library characterization, place and route, static timing, power, and electromagnetics, among several others. He also drove the first common compiler architecture for emulation and prototyping platforms.

Dr. Devgan is an IEEE Fellow, has written numerous research papers, and holds 27 US patents. He has won several awards, including the prestigious Phil Kaufman Award for his extensive contributions to EDA as well as the IBM Corporate Award and IEEE McCalla Award. Dr. Devgan serves on the boards of the Global Semiconductor Alliance and the Electronic System Design Alliance.

Dr. Devgan received a Bachelor of Technology degree in electrical engineering from the Indian Institute of Technology, Delhi, and MS and PhD degrees in electrical and computer engineering from Carnegie Mellon University.

Balajee Sowrirajan is the Corporate Executive Vice President and MD, of Samsung Semiconductor India Research (SSIR) - the hub of semiconductor innovation in India.

At SSIR, Balajee oversees the India operations of the Memory, System LSI, and Foundry business unit and drives both strategy and culture for innovation and inclusion. Balajee has played a pivotal role in paving the way for SSIR as a technology leader in the semiconductor industry in India, making it the largest Global R&D Centre for Samsung Semiconductor.

He has brought in excellence in designs while guiding the System LSI team towards the development of key components for Mobile and Automotive Electronics businesses. Similarly, the memory business continues to maintain its top market share for close to three decades now, while the Foundry business has been able to retain the position as the second largest foundry supplier in the world under his leadership.

With a Computer Science degree from BITS Pilani, Balajee has a corporate experience of over three decades. He started his career as a software engineer, before making the shift to VLSI (Very-large-scale integration) Design. Prior to SSIR, Balajee was associated with Texas Instruments, where he was elected as a Distinguished Member of the Technical Staff.

In his free time, Balajee loves to spend time with his family and has a passion for photography.

Dr. Alok Jain is a Vice President in the System Verification Group (SVG) at Cadence. He is leading the Xcelium Advanced Verification Simulation (AVS) program. His responsibilities include all aspects of the Xcelium simulator including Xcelum-ML, Fault Simulation, Mixed Signal and Multi-Core capabilities as well as other Xcelium Apps. Prior to this role, he worked in the area of Formal Verification, including Equivalence Checking and Model Checking. Dr. Jain has 25+ years of industry experience. He has 30+ technical papers in internal and external conferences. He has 10+ granted patents in the area of formal and functional verification. Alok received a Bachelor of Technology degree in Electrical Engineering from Indian Institute of Technology, Delhi and M.S and Ph.D. degrees in Electrical and Computer Engineering from Carnegie Mellon University, Pittsburgh, USA.

Matt Graham is Product Management Group Director in the System & Verification Group at Cadence leading the product management team responsible for  digital simulation and AI-verification.  Over his 20 year career at Cadence Matt has held a number of senior technical and leadership positions in the Applications Engineering, Product Engineering and now Product Management organizations.  Prior to Cadence Matt was an ASIC design and verification engineer at several fabless semiconductor companies.  Matt holds an Electrical Engineering degree from the University of Waterloo and is based in Ottawa, Canada. 

 

Ashish Mehra is a Vice President of R&D at Cadence, leading digital design implementation and AI/ML solutions at Cadence. He is driving Digital design implementation and Cadence AI/ML solutions, including Genus, Innovus, Cerebrus & JedAI on the most advanced and complex designs using advanced tech nodes.

With 23 years of industry experience, he has held senior leadership positions at Synopsys, Magma Design Automation, and Texas Instruments. Ashish holds a master's degree in VLSI & Microelectronics from IIT Kharagpur and is a leader, mentor, and innovator, driving customer success through his technical expertise and global team leadership.

24 years experienced in EDA, CAD & Design Implementation. Managing a physical design team in Intel CPU physical design Unit.

Muzaffar works as Senior Staff Engineer in MediaTek Bangalore. Muzaffar has close to 13 years of experience in Physical Design Domain. Muzaffar had graduated from College of Engineering, Trivandrum. Muzaffar started his career with Wipro Technologies and worked in Intel Malaysia before joining MediaTek.

Rajat Sachdeva is a VLSI enthusiast having 6 years of experience in the VLSI Industry. Currently Working with NXP Semiconductors as Physical Design Methodology Engineer. Prior joining to NXP, He has worked with Intel for 4 years in various roles.

Physical Design Engineer with an expertise in P&R, STA, Physical and Power Signoff. I have close to a decade of experience working on PAM and Coherent DSPs at the latest technology nodes. Outside of work, I have a passion for trekking and other outdoor adventures. I have recently taken an interest in photography and love to take my camera on a ride as I travel across these trails.

I am Sameer from Warangal district of Telangana state, India. I am a PDK Engineer at Intel and working on developing ASIC pdk collaterals development. I have around five and half years of work experience in the industry. I have been graduated from Kakatiya University, Warangal, Telangana state. My hobbies are playing cricket, badminton, spending time with family and friends.

Subhadeep is a Physical Design Engineer at Texas Instruments with 5+ years of experience in PnR, Low Power Signoff, Reliability and Physical Verification.

Having more than 20+ years experience in the semiconductor industry, both presilicon and post silicon with companies like ADI, AMD, ARM, Intel, I setup ProteanTecs in India and have been working there from the last 3 years.

Karthik Raju is a rising talent in the field of Physical Design engineering with four years of experience in the semiconductor industry. Currently serving as a Senior Physical design engineer at Marvell India PVT LTD. He earned his Bachelor’s degree in Electronic and Communication Engineering form Sri Ramakrishna Engineering College at Coimbatore, Tamil Nadu in 2020. Karthik began his career at Spicaworks India PVT LTD in 2020, where he worked on cutting-edge technology nodes (TSMC 3nm,5nm,7nm and 12nm) for clients Micron Technologies and NVIDIA. Outside of his professional work, Karthik likes to play Badminton. He participates in local tournaments and enjoys playing with friends and colleagues.

Mohammad Shoeb is A staff engineer from Marvell Technology Inc. He has a 7+years of experience in Physical Design with demonstrated history of working in lower nodes (TSMC5LPE, TSMC5FF, TSMC7LPP). prior to Marvell he Worked for Sevitech Systems Pvt Ltd. He has a Masters in technology from Aditya college of engineering, Andhra Pradesh. Apart from engineering he is into martial-Arts. he is a Karate black belt holder from Japan Shotokan Karate Do Kanninjaku Organization, INDIA. He spends his free time listening to music and travelling with friends.

CPU physical Design Engineer at Intel with 8+ years of experience. Masters in VLSI & Embedded Systems from NIT, Surat.

Ashish Mehra is a Vice President of R&D at Cadence, leading digital design implementation and AI/ML solutions at Cadence. He is driving Digital design implementation and Cadence AI/ML solutions, including Genus, Innovus, Cerebrus & JedAI on the most advanced and complex designs using advanced tech nodes.

With 23 years of industry experience, he has held senior leadership positions at Synopsys, Magma Design Automation, and Texas Instruments. Ashish holds a master's degree in VLSI & Microelectronics from IIT Kharagpur and is a leader, mentor, and innovator, driving customer success through his technical expertise and global team leadership.

Has total experience of 11 years on On-Chip PSI Signoff, Methodology and Product Engineering for 2D, 2.5D, 3DIC and Analog Mixed Signal Designs. Currently Working as Senior Manager in Samsung Semiconductors India Research Bangalore, Foundry team Leading On-chip PSI Methodology and Signoff team.

Anuradha is a Senior Staff Engineer at Samsung. She has 7 years of experience in physical design and works as a Methodology engineer.

Arpan is an Associate Staff Engineer at Samsung with around four years of experience in on-chip Power and Signal Integrity (PSI). As part of the Samsung Foundry Physical Design team, he handles methodology and automation for PSI analysis.

Abhinav Gaur has 6 years of experience in the VLSI Industry. Currently Working with NXP semiconductors as EMIR Methodology Engineer.

Lakshmi Narayanan is a VLSI professional with 19+ years of experience in the semiconductor industry. She specializes in physical design implementation of semiconductor designs. She is currently a Senior Technical Staff Engineer at Microchip Technology. Her current interests are advanced packaging, 2.5D/3D heterogenous integration and related flows.

Bharathwaj is a Principal Design Engineer at Microchip Technologies. With over 14 years of experience in the Semiconductor Industry, he has worked on chips for mobile, networking, and computing.

Apoorv is a Group Manager at STMicroelectronics, with over 17 years of experience in RTL design through physical implementation. Currently, he leads the Synthesis and STA team for Automotive products in the MDRF-ADP team at ST. He has been successful in defining and deploying flows for synthesis and STA related to in-house P28 technology.

T Somalatha, joined as NCG in 2022 in Connectivity Physical design team. She has expertise on chip reliability analysis like IR, EM, ESD and Inrush analysis and wire-bond packages. She has worked on multiple SoCs by contributing through robust reliability closure methodologies. She is always fascinated about new things - let it be a new methodology, flow or implementation and different Si-node. She has completed B-Tech in 2022 in Electronics and Communication Engineering. Her hobbies are Swimming, Skating and Trekking.

Shourya has been working with Marvell as a STA-CAD Engineer since 2021. Before joining Marvell he has worked on RTL-to-GDS CPU/GPU implementation flow in ARM.

Aditya Mathur is a Senior Design Engineer at Arm.

This is Rishabh Singh, I hold a Masters in RF Design and Technology from IIT Delhi and currently working as a Digital Engineer at TI for the past 3 years. I have expertise in Power/IR signoff and EMIR flow development.

Ashish Mehra is a Vice President of R&D at Cadence, leading digital design implementation and AI/ML solutions at Cadence. He is driving Digital design implementation and Cadence AI/ML solutions, including Genus, Innovus, Cerebrus & JedAI on the most advanced and complex designs using advanced tech nodes.

With 23 years of industry experience, he has held senior leadership positions at Synopsys, Magma Design Automation, and Texas Instruments. Ashish holds a master's degree in VLSI & Microelectronics from IIT Kharagpur and is a leader, mentor, and innovator, driving customer success through his technical expertise and global team leadership.

Lead Engineer in TI. Part of Application Specific Microcontroller team.

Saravanan Arulmozhi currently holds a position at Microchip, specializing in Design for Testability (DFT) methodologies. With 12 years of experience in DFT, Saravanan has significantly contributed to the semiconductor industry, having worked with industry leaders such as Qualcomm and AMD.

ASIC design and methodology engineer with over 15+ years of experience in architecting implementation and sign-off flows, defining methodology for high performance wireless and mobile chips in companies like Qualcomm, Intel and Texas Instruments. Part of GCAD team at Qualcomm, involved in managing & development of formal verification methodologies (equivalence checking for RTL to GDSII) for next generation mobile, Auto, wireless, Wi-Fi SoCs. Received Masters in Microelectronics and VLSI design from Indian Institute of Technology (IIT) Kharagpur in 2006

Amithanand is a Hardware Engineer at Intel, working on CAD EDA Tools.

Pervez Garg (MGTS) is leading Processors DFT team at Texas Intruments. He has an experience of 14 years in defining novel DFT architecture for low power test, optimized test cost, DFT implementation for mixed signal designs and post-silicon debug. He holds Bachelor’s degree in EEE from BITS Pilani.

Satya Bhamidipati has more than 16 years of experience in the semiconductor industry. Presently, working with Infineon Technologies as a DFT Principal Design Engineer. Earned his Master's degree in Systems and Control Engineering from the Indian Institute of Technology, Bombay. Satya Bhamidipati has obtained 2 patents in the field of Design of Test.

Jemin is a Digital Design Engineer in the Radar and Analytics (RAP) DFT Team at Texas Instruments India Pvt. Ltd since July 2023. He has a BTech Degree in Electrical and Electronics Engineering from Birla Institute of Technology and Science, Goa. Currently he works on the implementation of test architectures for Radar automotive and industrial SoCs.

Rupesh is currently a DFT Design Engineer in Radar team at Texas Instruments Inc., Bangalore. He completed his graduation in Microelectronics and VLSI from Indian Institute of Technology Bombay in 2021. His areas of interest include scan insertion and ATPG.

Hrithik Sahni, is a digital design engineer in the RAP (Radar & Analytics Processor) DFT team at Texas Instruments India Pvt. Ltd. He joined TI in 2022 after completing his B.Tech in Electronics and Communication Engineering from Netaji Subhas Institute of Technology (NSIT) Delhi where he was the academic gold-medalist of his batch. He has worked on different aspects of DFT like memory test, ATPG, test and functional safety.

Currently Working at Google as CPU Physical Design Engineer. Having 13+ years of experience in PD and signoff. Taped out 20+ chips ranging from 28nm to 3nm technologies on multiple designs/Products like Networking, WIFI,IoT,Automotive, Mobile, CPU, Display,GPU, Peripherals, and DDR.

Working as a DFT Methodology engineer in Google, owing entire Scan Stitching flow and related methodologies. Have been working on DFT for more than 7 years, specially interested in solving problems related to Power, PNR, & Coverage. Authored 2 patents on low power DFT I have pursued my BE from Jadavpur University in Electronics and Tele-Communication.

Ashish Mehra is a Vice President of R&D at Cadence, leading digital design implementation and AI/ML solutions at Cadence. He is driving Digital design implementation and Cadence AI/ML solutions, including Genus, Innovus, Cerebrus & JedAI on the most advanced and complex designs using advanced tech nodes.

With 23 years of industry experience, he has held senior leadership positions at Synopsys, Magma Design Automation, and Texas Instruments. Ashish holds a master's degree in VLSI & Microelectronics from IIT Kharagpur and is a leader, mentor, and innovator, driving customer success through his technical expertise and global team leadership.

Sivaraman P, is an alumnus of Anna University with a Master's degree in Applied Electronics, holds the position of Senior Manager in the CPU Design team at Intel Technology India Pvt Limited. With a career that spans over 19+ years, he has emerged as a venerated figure within the semiconductor industry. His professional odyssey commenced at Cadence, followed by a pivotal role as a GPU Physical Design Engineer at Intel. His expertise was further refined during his tenure at TCS in Seoul, Korea and subsequently at Qualcomm in Bangalore, where he excelled in physical design and project management. Elevating to the role of Principal Engineer at Eximius Design, Sivaraman showcased his extraordinary talents, which paved the way for his return to Intel in June 2021 to lead the CPU Physical Design team. His leadership has been marked by a succession of triumphant tape-outs, including Intel/Arm CPUs, Intel/Imagination GPUs, HBM, DDR and various other designs, demonstrating his mastery over a range of advanced technology nodes from Intel's 18A and 20A processes to TSMC/Samsung 2nm processes. Renowned for his dynamic leader in excellence and camaraderie among his colleagues. He is an active participant in leadership forums and serves as a driving force within an AI consortium at Intel, evidencing his profound comprehension of AI standards and his adeptness in scripting languages. Sivaraman's unwavering dedication to program management, coupled with his comprehensive skill set, ensures the consistent delivery of superior solutions. His contributions have cemented his status as a luminary in the challenging and constantly advancing field of CPU Physical Design.

Anjaneyulu B is an CPU Physical Design Engineer, distinguished by his Master's degree from the eminent IIT Kanpur and a dynamic three-year tenure in the semiconductor industry. His expertise is marked by a mastery in low-power design, a discipline critical for the innovation of energy-efficient in CPU design, is now keenly poised to delve into the realm of Artificial Intelligence (AI). He is well-equipped to embrace the complexities of AI. Anjaneyulu's prowess extends to the intricate processes of synthesis and advanced place-and-route (APR), where his contributions have significantly enhanced the performance and reliability. His work on Intel's revolutionary 18A ,20A and Intel 4 nodes stands as a testament to his capability to navigate and excel within the most advanced technological landscapes, His proficiency in signoff flows has been instrumental in elevating chip designs to meet rigorous production standards. Anjaneyulu's technical acumen is further amplified by his adeptness in scripting languages such as Tcl, Perl, Python and Shell, which he has utilized to automate and refine design processes, thereby enhancing efficiency and precision.

Physical Design Engineer with an experience of 6+ years in the VLSI industry.

Sagar has 13+ years of Physical Design experience working at Qualcomm, Oracle, Samsung Austin R&D Center (SARC) and currently working at SSIR. He holds bachelor degree from IIT Kharagpur and masters degree from Texas A&M University (TAMU). Participated & contributed to multiple international tech conferences and holds a patent on design testing methodology. His hobbies include playing table tennis and TPS video games.

Ajay has 6+ years of physical design experience working at Einfochips-an Arrow company and currently working as associate staff engineer in Samsung Semiconductor India research. His hobbies include playing volleyball and sketching portraits.

Sarat Chandra Salihundam Senior Member Technical Staff, IDC Cores, AMD. Sarat Chandra is a Senior Member Technical Staff at AMD, responsible for delivering optimal flows for the physical implementation of CPU designs. In his current role at AMD, he explores various PPA enhancement techniques and methodologies to build the best possible recipe for CPU designs to meet challenging goals. He has 15 years of experience in the domain of physical design. Prior to joining AMD, he was with Intel where he led the execution of complex designs in Server and IoTG products. He holds a Master degree in Microelectronics from BITS Pilani.

Akshat Shah is the Group Director for Virtuoso Custom design and Spectre simulation platforms, responsible for solution deployment and product engineering. His team is driving and deploying some key Cadence technologies including Spectre X, Virtuoso RF and the Virtuoso advanced node solutions. He has been working at Cadence since 2004.

Kishan Chanumolu has two decades of experience in architecting and defining layout methodologies for High Speed Analog & Mixed Signal Interface IPs including ESD protection design for DDR, ONFI and Serdes PHYs. He earned Diploma in Electronics from NTTF (Nettur Technical Training Foundation) and PG level Advanced Certification in Micro and Nano Electronics from Indian Institute of Science (IISc). He had 4 patents in ESD and layout fields and currently employed as Principal Engineer in Micron, Bengaluru, responsible for all the Layout activities for ASIC ONFI, DDR & Serdes phys.

Danish has received his B.Tech degree in Electronics and Communication from Jamia Millia Islamia, New Delhi and Masters in Microelectronics from Bits Pilani. In past he had worked with Cadence, NXP and Maxlinear as an EDA Developer for custom IC tools and Methodology. From June 2020 he is working with Western Digital Bangalore India as a Technologist, leading an overall effort for Analog and Mixed Signal CAD development and automation. His area of interests includes Custom IC Analog and Mixed Signal Design and Layout Automation, EDA methodology development, and Machine Learning and AI techniques for EDA.

Nisha has over 15 years industrial experience in STMicroelectronics. Currently working as Staff Engineer, she is an expert in Layout of Analog and Mixed Signal IPs like Data Convertors, PLLs etc. Additionally, she has contributed significantly to development and improvement of CAD Views Generation and Verification Methodologies.

Urvashi Jindal is working as Senior Lead Design Engineer in Design Enablement department of NXP. She has an experience of over 10 years. She looks into the best available market solutions for Analog Backend for mature to advanced nodes.

Shanmuganarayanan S (Shanmuga) is the layout engineer for the Custom India team having 9+ years of industry experience, across range of products including high speed (Gig Switches, USB Repeaters, Re-drivers) & DDR and Oscilators. He is also very avid automation & tool creator. He has presented in multiple conferences.

Atif Mohd is an Engineering Manager leading the Design Support and Application team in Intel India, while technically focusing on layout methodology towards TFM enablement and rollout for the global Analog and Mixed signal teams at Intel. His recent focus is on enabling the layout TFM for the most recent advanced node technologies. In this role, he closely collaborates with the EDA partners outside Intel towards state-of-the-art solutions. He has nearly 18 years of experience in the AMS and digital layouts, methodology and CAD fields. Prior to Intel, Atif has worked at STMicroelectronics and Synopsys in their IP development teams.

Amit is a Senior Staff Layout Manager at Qualcomm. He has over 17 years of experience in RF and analog layout. Amit has a Bachelor’s degree in Electronics and Communication Engineering from Haldia Institute of Technology, West Bengal.

Dhanesh Kumar is Senior Manager in CE-AMS FIP Analog Layout. He has over 17+ years of Experience in AMS and IO Layout Design. He holds a Master’s Degree from BITS, Pilani. Working with Marvell for 3+ years. Before Marvell, he worked with Rambus, Global Foundries, and IBM. Has worked across various nodes from 180nm to 2nm on High-Speed blocks.

I have 9+ years experiences in Custom layout and CAD. Process and Methodology Team.

Vipin Kypada Chandran is a seasoned professional in the VLSI design industry, with over 13 years of expertise in memory compiler layout and custom layout design. He obtained a B.Tech degree in Electronics and Communication Engineering from CUSAT (Cochin University of Science and Technologies) in 2010 and began his career as a memory layout engineer at Broadcom. In 2015, he joined SSIR, where he continues to apply his extensive knowledge and skills to the field.

Santosh Kumar Khyalia received the B.Tech. degree in electronics and communication engineering from Rajasthan Technical University, Kota, India, in 2010, MTech. degree in communication engineering from the Indian Institute of Technology Delhi, Delhi, India, in 2014, and joint PhD degree from IIT Bombay and National Taiwan University, Taipei Taiwan in 2024.He is currently working in onsemi India Pvt. Ltd. as a Staff Engineer (Analog). He is author of more than 10 IEEE journal and conference papers. His current research interests include analog, RF, and millimeter-wave circuits for wireless transceivers/RF CMOS ICs, such as LNAs, mixers, oscillators, PLLs, frequency multipliers, and filters.

Basavaraj is a Senior Principal CAD Engineer at onsemi with over 20 years of experience in VLSI CAD flows, design verification flows, and the design, probing, and testing of integrated chips. His key area of expertise is Functional Verification of Analog, Analog Mixed-Signal, and Digital design flows, VLSI Full-Custom Flow, and Reliability analysis. Previously, he worked with Cypress Semiconductors, Cadence Design Systems, Calogic, and BEL. He holds a bachelor’s degree in Electronics and Communications from Karnatak University and an MBA in Entrepreneurship and Business Enterprise from EDII, Gujarat.

John O’Donovan is a Distinguished Engineer for the Spectre simulation platform at Cadence. John oversees the development and support of both the Spectre X and Spectre APS simulators. He also leads both the R&D and product engineering teams working on the Voltus-XFi transistor-level EMIR solution. John has been working at Cadence since 1998 and graduated from University College Cork, Ireland.

Jim Godwin has 7+ years of experience in Simulations and Frontend EDA Solutions. His main interests are AMS, Maestro, and Analog Frontend EDA solutions.

Ankit is a Member of Technical Staff at STMicroelectronics, where he works on Clock Generation Circuits and Analog-to-Digital Converters. He joined the TDP Department of STMicroelectronics in 2015 and has been involved in designing and developing Analog Mixed Signal Circuits. Before joining STMicroelectronics, he worked at Cosmic Circuits, focusing on 8GHz Serial Links. Ankit holds 8 US patents and has a B.E. degree in Electronics and Communication Engineering from the University of Delhi.

Debajit Kumar Das is an Analog Design engineer specializing in Analog Mixed Signal Design. He completed his Bachelor's degree in Instrumentation & Electronics Engineering from Jadavpur University in Kolkata. In 2019, Debajit embarked on his professional journey with Texas Instruments as a New College Graduate, where he made significant contributions to the design of various analog blocks, including OPAMPs, DACs, and ADCs for complex analog mixed signal chains. In 2022, Debajit joined NXP Semiconductors, where his expertise further extended to the development of ADCs for Automotive Radar Products. Demonstrating his versatility and technical acumen, he was entrusted with the challenge of design migration across different technologies. Debajit successfully established an entire schematic migration flow from ground up, enhancing the process to produce high-quality designs and testbenches ready for simulation. Throughout his career, Debajit's innovative contributions and dedication to excellence have distinguished him as a valuable asset in the field of analog mixed signal design.

Incoming MS Electrical Engineering graduate student at Columbia University in the City of New York. Worked as Analog Flows Engineer at STMicroelectronics, India.

Atul has been working with STMicroelectronics for the last two decades. He currently holds the position of Senior Group Manager and Senior Member of Technical Staff. His responsibilities include PDK development, CAD Flows, and methodologies for ST technologies. He specializes in Analog-Full custom Flow development, focusing on design methodologies, layout development, and verification. His expertise includes fast spice simulation engines, EMIR methodologies, parasitic extraction, and layout productivity. Atul has over 100 paper publications in international conferences. He also serves as a member of the Technical Program Committee for multiple conferences, including DAC and ISQED.

Mr Nitin Pant received B.E Degree from Delhi College of Engineering (now DTU). He has over 14 years of experience of VLSI industry and is currently part of SoC Analog & Mixed Signal Verification in NXP- India Design Centre, Noida. He is experienced in developing Analog Architecture at SoC Level, AMS and Full Chip SPICE verification of complex mixed signal SoC’s having various subsystem such as – Power management, Data converters, Clocking and high speed peripheral interface at both Chip Top and Subsystem level. He holds 6 patent grants, multiple IEEE papers, and numerous international publications in the field of AMS design architecture and methodology. He has represented NXP in multiple design conferences such as, CadenceLIVE, SNUG, DVCon, etc. Outside Working hours, Nitin likes to spend quality time with family and friends. Nitin is also fond of travelling and adventure sports.

Kaustuv Sahu works as an EDA Engineer in Analog Frontend Applications Team at Texas Instruments. He joined TI as an NCG in 2022, after completing his B.Tech in Electronics and Communication Engineering from Delhi Technological University

Working in Samsung foundry analog design QA team.

Shreya Sinha is an EDA Engineer at Texas Instruments. She joined TI as a new college graduate after completing her B.Tech from Jadavpur University, Kolkata.

Working as Senior CAD engineer with 4.5 years of experience.

6+ years of experience in SRAM-ROM CAD Domain at NXP Semiconductors Bengaluru.

Pavan Vernekar with more than 9 years of experience in VLSI industry, works for Infineon Technologies as Staff Engineer and into AMS verification domain. After pursuing Masters in VLSI from Manipal Institute of Technology - Manipal, started career as AMS Verification and Analog Integration Engineer for SoC’s in Microchip Technology, Currently Working for Infineon Technology in serving for deliveries of AMS verification for SoC’s for segments like Automotive MCs, power & sensor systems.

Raghavendra Chavan with more than 11.5 years of experience in VLSI industry, works for Infineon Technologies as Senior Staff Engineer and into AMS verification domain. After pursuing B.Engg in EEE from KLE Institute of Technology - Hubli, started career as Spice Modeling Engg in Sankalp Semiconductor’s, Currently Working for Infineon Technology in serving for deliveries of AMS verification for SoC’s for segments like IoT MCs, power & sensor systems.

Experienced professional with over 13 years in the industry, specializing in the characterization of standard cell libraries, I/O, and analog IPs. Currently serving as SMTS at GlobalFoundries. Passionate about innovation and excellence in semiconductor technology.

Filzer is part of the Product Engineering team at Cadence focusing on the Liberate Characterization Portfolio. He was part of the Field Application Engineering team at Synopsys and Magma, creating IP characterization solutions for customers, and has also worked for Arm and TI in consulting role prior to that.

Having around 7 years of experience in Standard cell Characterization. Worked on different tools like Liberate, Tempus, Voltus and Redhawk. Did masters in VLSI Design from SRM university, Chennai. My Native place is Prayagraj, UttarPardesh.

Senior Design Engineer at ARM, I work in logic DE Team.

Shreyash Tripathi has completed his graduation in Electronics & Communication and is currently working as Tech Lead with STMicroelectronics with 5+ years of experience. He is responsible for design, characterization, and validation related activities for Embedded Memories (SRAMs).

Nick Heaton, Distinguished Engineer at Cadence Design Systems responsible for SoC Verification. Nick has a long track record of design and advanced verification of Arm systems since the late 1990s, he spent 15years in SoC design and more than 20 years in advanced verification, heavily involved in Cadence’s relationship with Arm around AMBA VIP, coherency verification, performance verification and is the architect of the Cadence System VIP suite of tools for advanced SoC verification.

Niti has 6+ year of experience in Analog Mixed Signal Domain. She is working with NXP Semiconductor in Design Enablement as Engineering Support Engineer supporting the Analog and AMS Team globally in NXP. Niti has a Masters degree in VLSI Design from SOIS Manipal University and Bachelor Degree from SSCET Chhattisgarh. Her interest areas are Analog Mixed Signal Verification, modelling and automation.

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Ankit has been working in the field of end-to-end formal verification and architectural formal verification since 2011. He joined Marvell Technology in December 2020 as a formal verification expert, and he has been implementing end-to-end formal verification on various SSD and custom processor designs. Before joining Marvell Technology, he worked for Oski Technology (now NVIDIA) for about 10 years. During his time at Oski Technology, he collaborated with various customers to implement end-to-end formal verification on their designs and also provided training to their teams in this methodology. Ankit holds a B.Tech degree in Electrical Engineering from IIT Kanpur.

I have been with Samsung Semiconductor India R&D for the past 3.5 years in SoC Design Verification team and currently working as Staff Engineer. I am Skilled in System Verilog, UVM, Application-Specific Integrated Circuits (ASIC), Digital VLSI Design, verilog and C Programming. I have keen interest in working on upcoming trends and technologies in the field of Digital VLSI Design. I have pursued M.Tech focused on VLSI and Embedded systems from Sardar Vallabhbhai National Institute of Technology, Surat.

Anant is a Design Verification Engineer in the Radar SoC team at Texas Instruments. As part of the Functional Safety team, he has been responsible for handling Fault Injection Campaigns and creating Functional Safety (FuSa) documents for low-power RADAR. Currently, he is working on the verification of the 3rd generation RADAR Hardware Accelerator IP. He holds a B.Tech. from the Indian Institute of Technology (BHU) Varanasi.

Aniruddha is a semiconductor professional currently serving as a Senior Engineer at Samsung Semiconductor India Research (SSIR). He has 2.5 years of experience at Samsung, working in the Safety team. His areas of expertise include UVM, SV, and scripting. He has a B.Tech degree from B.M.S. College of Engineering.

Aniket Bhatia is a Formal Verification Engineer at NVIDIA. He graduated from National Institute of technology, Tiruchirappalli in Electronics and Communications Engineering. He has worked with Formal Verification Techniques including Data Path Verification.

Pruthvi is working as an Engineer in the Design Verification team at Analog Devices. He has received the B.Tech. degree in Electronics and Communication Engineering from the National Institute of Technology, Rourkela, in 2021, and the M.Tech. degree in Microelectronics and VLSI from the Indian Institute of Science (IISc), Bengaluru, India, in 2023.

System on Chip (SoC) Design Verification Senior Staff Engineer with 7+ years experience working on wide range of ASICs on latest technology nodes: Application Processors, Mobile Co-processors, Automotive, ADAS, XR (AR/VR/MR), HPC 3DIC and AI/ML Accelerator Data Center chiplet based 2.5DIC SoCs at Foundry Design Services (Hardware) division at Samsung Semiconductor. Actively contributing to cutting edge ASIC/Silicon ecosystem R&D with 15+ paper publications and 3 Best Paper and 2 Best Poster wins across industry leading VLSI technical conferences.Electronics major from National Institute of Technology, Warangal with a keen interest in digital electronics and the current trends and innovations in semiconductor industry.

I'm Sahana, working as a tech leader in STMicroelectronics. I worked on verifying Ethernet protocol in RTL & GLS verification, where I verified different speed modes of ethernet (1G, 2.5G.5G.10G, &10BASET).

Asjad Fahmi is a design verification engineer at STMicroelectronics. He works on the verification of Debug & Trace IPs, network switch safety, and new communication IPs such as 10Base-T and high-speed Ethernet protocol.

Im sahana, working as a tech leader in STmicroelectronics. I worked on verifying Ethernet protocol in RTL & GLS verification, where i verified different speed modes of ethernet(1G, 2.5G.5G.10G, &10BASET)

I am currently working as a senior dft design engineer in NXP semiconductor and have 3 years of experience. I have worked upon ATPG ,GLS, spyglass and scan insertion.

He is working as Senior Manager in SSIR in SoC Development. He has got 15 years of experience in IP, SoC level. In the past he served for LSI, Broadcom, Synopsys.

Been part of Semiconductor industry for the past two years. Born and brought up in Kakinada city. Did a dual degree from IIT Madras in the field of Electrical Engineering.

Lopamudra Pattanayak is currently working as Senior Staff Engineer in Samsung Semiconductor India Research, Bangalore. She has been working in the VLSI Industry for 9 years. She started her career in ASICZEN technologies, where she worked on clients like Qualcomm and Rambus. During this tenure she worked in VCODEC Verification and PCIEIP verification. She worked in Wipro for 3 years, Intel as Client and involved mostly inPCIE IP Verification. She moved to Samsung in 2022. In this she has been involved in SoC Verification of PCIEfor various Automotive SoCs. She did Master’s Degree in VLSI Design and Embedded Systems from KIIT University, Odisha.

Born and brought up in Lucknow, I am currently working with Google, Bangalore as Silicon Design Verification Engineer for more than 2 years now. Previously, I was with Blaize (formerly ThinCi Semiconductor), Hyderabad for 3 years. I have completed my Masters in Integrated Circuits from University of Hyderabad, Hyderabad. I resonate with women empowerment strongly and work as a Connect Pillar Lead at Google, focussing on creating better opportunities and catalyze DEI.

Vivek Upadyaya has been working VLSI industry as a functional DV engineer for past 18+ years. Having started his career in Wipro Technology, followed by Imagination Technologies in initial 5 years, he has been working with Qualcomm India GPU DV team for last 13+ years. He has extensively worked on different aspects of GPU Core DV during this stint over multiple generations of Adreno GPU lineup since 2011. He has handled multiple projects with complex TB development, debug and coverage closure. He has Bachelor's degree in Electronics & Communication Engineering from VTU Belgaum.

Amita Trisal is the Director of Engineering at Qualcomm, where she has been leading the GPU IP Verification team since 2011. With over 20 years of industry experience, she has made significant contributions to the evolution of Qualcomm GPU Technologies by architecting and delivering verification strategies for complex Multimedia cores and functions. She holds a master’s degree in Microelectronics. Prior to joining Qualcomm, she gained 7 years of work experience at STMicroelectronics and Texas Instruments, where she specialized in delivering high-quality Automotive products.

Pattan Farooq Khan is an accomplished semiconductor professional, currently serving as an Associate Staff Engineer at Samsung Semiconductor India Research. Specializing in Universal Verification Methodology (UVM) and functional verification, he is also certified as a Functional Safety Engineer Level - 1 under ISO 26262:2018 (Road Vehicles - Functional Safety). Pattan Farooq Khan is also pursuing an MTech in Microelectronics at BITS Pilani.

Working as EDA Tools Software Engineer at Intel India.

T Chethan is a Performance Verification Engineer working at Samsung Semiconductor India Research. He is an Engineering graduate from JSS Science and Technology, Mysore specialized in Electronics and Communication.

Ashutosh is a seasoned SoC Verification Engineer with 10 years of experience in the field of SoC Verification and Emulation. He has previously worked with companies such as Qualcomm, NXP Semiconductors, Synopsys, and HCL Technologies. Currently, he is employed at STMicroelectronics where he has honed his skills in various aspects of SoC development and Verification, Emulation Model Build, and Bring-up. He is proficient with emulation platforms such as Palladium, Veloce, and ZEBU and skilled in using JTAG-based debuggers and Lauterbach T-32 for efficient Presilicon Use case Verification. Ashutosh has extensive experience working with ARM Cortex and PowerPC architectures and holds a B.Tech in Electronics and Communication Engineering.

12+ years in IP /SOC level Design verification experience. Worked CSI/DSI/Ethernet/Interconnect verification. Working with Cadence SYSVIP from past 1.5 years.

Avinash is an SoC Verification Engineer with 13 years of experience in IP and Subsystem SoC Verification. Over the years, he has contributed to significant projects at renowned companies such as Sandisk, Broadcom, Intel, and AMD. He holds a B.Tech degree in Electronics and Communication Engineering and a PG Diploma in DVLSI from CDAC.

Jainender Kumar has total of 11 years of experience in the field of functional verification with more than 5 in the field of SoC Interconnect verification.

Debasis Mishra is currently working as a Senior Staff Engineer in Samsung Semiconductor India Research, Bangalore. He has 9+ years of experience in Design Verification. He started his career with Wipro Technologies and worked for various client projects. During these tenure he worked in multiple SOC and IP verifications projects. He worked in Wafer Space Semiconductors for 4years at Qualcomm Client location. He joined SSIR in 2022 and is involved with few Automotive projects. He worked in verification of Safety IPs and safety verification in Automotive SoCs. He is a certified Functional Safety Engineer Level 1. He did his MTech in Communication Systems Engineering from KIIT University, Bhubaneswar, Odisha. 

Ayushi is a System on Chip (SoC) Design Verification Engineer currently working in the Sitara MPU division at Texas Instruments. With over 5 years of experience, she has worked on a wide range of ASICs including those for automotive and industrial applications. Prior to her current role, she gained experience at Micron Technology and Western Digital. Ayushi holds a master's degree in Microelectronics from BITS, Pilani, and has a keen interest in digital electronics as well as staying updated on the latest trends and innovations in the semiconductor industry.

I am Vinay. I work at Samsung Semiconductor and have 18 years' experience and worked in Embedded Software development, SoC Performance verification, Competitive analysis.

Taranjit Kukal is Senior Architect, Product Engineering at Cadence Design Systems, responsible for Design Capture and Analysis offerings for PCB and Package Design.

In the past, he led Co-design flows, Hi-Speed flow, PSpice and IP-modeling development at Cadence. Prior to joining Cadence, he worked at HCL Ltd. doing embedded designs and analog designs. 

He graduated from IIT, Delhi in Electrical Engineering in 1990. He has more than 35 EDA patents granted in US patent office and several papers in conferences.

Praveen is an experienced PCB and IC package design engineer with over 15 years in the electronics industry. Throughout his career, he has excelled in designing complex printed circuit boards (PCBs) and integrated circuit (IC) packages for various sectors, including consumer electronics, telecommunications, and avionics industries. He worked with Intel (AXG), Maxlinear, Accord Software, Sienna ECAD prior to Achronix. He received multiple awards for innovation recent one is Distinguished Invention Award 2022 at intel. Praveen proficient is Cadence Allegro, Altium Designer, and Mentor Graphics, and is skilled in advanced design techniques.

Bharath Kumar is a Lead Research Engineer at Hyundai Mobis. He is specialized in Signal Integrity, Power Integrity and High-Speed Board Designs.

Naveen Sundaramurthy is a senior engineer with 6 years of professional experience in signal and power integrity analysis. Currently, he works at Valeo India Pvt. Ltd. He completed a Master of Engineering degree in VLSI design in 2016. He has experience in high speed signals and high power layout guidelines. Experience simulating signal and power delivery networks at both the PCB and system levels. In addition, he has experience dealing with major interfaces like Multi-Gig Ethernet, MIPI, GMSL, LPDDR, PCIe, USB and others.

Santhosh Ramasamy: Santhosh has 15+ years of experience in PCB Layout Designing and Package design, PCB 3D layout simulation, DFM, DFA & DFT for PCB. As a PCB design engineer, I have good experience in multi-layer PCB, RF Design, very high-speed designs up to 40 GHz, high current power card designs, split power plane techniques, Blind and buried via Technologies, Gerber output generation & Validation, NC drill generation, penalization, taking care of all Signal Integrity Issues, EMI & EMC.As a Package design engineer working on various packages, New silicon application note development, and pinout definition.

I am a seasoned PCB Design Engineer with over 17 years of experience, specializing in the design of ATE boards, including probe cards and final test boards across various tester platforms.

I have around four years of experience in IC Packaging at Intel India Pvt. Ltd. Before that I completed one-year internship in Post Silicon Validation at Intel during the final year of M.Tech. I have done M.Tech in “VLSI & Embedded Systems” from IIT Patna, and B.Tech in Electrical and Electronics Engineering from NIT Sikkim. My current job role involves driving end-to-end development for substrate design from concept through tape-out and implementing physical layout and routing of the package design. I also perform substrate fit and routing studies to establish design, performance, and cost trade-offs. I work closely with silicon and hardware teams to optimize silicon-package-board performance and pinout. I am also involved in defining substrate design rules, conducting internal and external reviews, analyzing data, and resolving DRCs to optimize package design.

Anusha is a Platform Hardware Design Engineering Manager at Intel, with over 13 years of experience in IC packaging design. She is currently leading a team of engineers at Intel in developing product package solutions. Previously, she worked with semiconductor-based companies on IC packaging design throughout various phases of ASIC development, providing continuous support for IC package design. Anusha has experience in Flip chip packages and Wire Bond package designs. She holds a degree in Electrical and Electronics Engineering (BE).

I have 12+ years of experience in PCB designing. I have good expertise on High-speed boards, High power boards, HDI boards, RF boards and Flex boards. I am currently working as Lead PWB designer in Qualcomm.