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Best Presentation and Poster Winner

BEST PRESENTATION WINNERS

CUSTOM AND ANALOG DESIGN: IMPLEMENTATION

  • Uncovering Parasitics Bottlenecks and Faster Design Closure with Early In-Design Parasitics Analysis Using Virtuoso EAD

    - Western Digital

Danish Shaikh, Western Digital

Sujit Swain, Western Digital

Narayana Hegde, Western Digital

Yashesh Kacha, Western Digital

Sana, Western Digital

Sethupathy Balakrishnan, Cadence

CUSTOM AND ANALOG DESIGN: VERIFICATION

  • Boost Productivity Working with Virtuoso ADE Verifier - Texas Instruments

  • Shreya Sinha, Texas Instruments
  • Keerthi Guntupalli, Texas Instruments
  • Angelika Keppeler, Texas Instruments
  • Walter Hartong, Cadence

  • IP CHARACTERIZATION

    • TCAM Characterization Using Cadence Liberate MX - Marvell

  • Dan Lieberman, Marvell
  • Harsh Gupta, Cadence
  • Helen Shi, Cadence
  • Filzer Kummudiyil, Cadence

DIGITAL DESIGN ADVANCEMENT WITH AI

  • A Novel Approach for Total Power Reduction in a High-Frequency Design with ML-based Cadence Cerebrus

    - AMD
  • Sarat Salihundam, AMD
  • Sabeesh Balagangadhran, AMD
  • Neeraj Dwivedi, AMD
  • Abhishek Guggari, AMD
  • Safrina Mohammad, Cadence
  • Shyam Sundar A, Cadence

DIGITAL DESIGN AND IMPLEMENTATION

  • Innovus Glitch Power Optimization Using Joules Xreplay Flow - Broadcom

  • Tejas Bhalla, Broadcom
  • Vaibhav B P, Cadence
  • Sharad Bhushan Jha, Cadence
  • Anmol Khandelwal, Cadence

  • DIGITAL FRONT-END DESIGN AND TEST

    • Breaking Test Cost Barrier for Safety Critical Automotive Designs Targeting Zero DPPM - Texas Instruments

  • Nitesh Mishra, Texas Instruments
  • Rupesh Lad, Texas Instruments
  • Hrithik Sahni, Texas Instruments
  • Ravi Kumar, Texas Instruments

DIGITAL SIGNOFF

  • Enhanced State-Propagation-Based Vectorless  IR-Drop Analysis Emulating Realistic Silicon Behavior - Texas Instruments

  • Rishabh Singh, Texas Instruments
  • Subhadeep Ghosh, Texas Instruments
  • Ruchin Gupta, Cadence
  • Sushant Sharma, Cadence

  • ADVANCED VERIFICATION METHODOLOGY

    • Unleashing UCIe Verification by Capturing Complex AI Dataloads Using Xcelium NDie Simulations for Multi-Chiplet SoCs - Samsung

  • Harshal Kothari, Samsung
  • Vinay Swargam, Samsung
  • Jerin M Jose , Samsung
  • Jasobanta Sahoo, Samsung
  • Madhukar Ramegowda, Samsung
  • Chethan Kumar G, Cadence

    • PERFORMANCE AND SMART BUG HUNTING

      • Maximizing Verification Efficiency Using the Synergy of AI and Machine Learning - Qualcomm

    • Amita Trisal, Qualcomm
    • Vivekananda Upadyaya P, Qualcomm
    • Ashwani Kumar, Qualcomm
    • Mayank Agarwal, Qualcomm
    • Rajdeep Parmar, Cadence
    • Sundararajan Ananthakrishnan, Cadence

      • HARDWARE AND SYSTEM VERIFICATION

        • Emulation-Based Fault Campaign: The Pandora Box of Lightning Fast Safety Verification

          - Samsung

      • Chandra Has Dondapati, Samsung
      • Prashantkumar Sonavane, Samsung
      • Debasis Mishra, Samsung
      • Garima Srivastava, Samsung
      • Naveen Kumar V, Cadence

      • PCB AND SYSTEM DESIGN AND ANALYSIS

        • Sigrity X Aurora Topology Extraction Workflow, and TopXp Workbench - Infineon

      • Santhosh Rangasamy, Infineon

      • COMPUTATIONAL FLUID DYNAMICS

        • Efficient VOF Simulation to Capture Windage Losses Validation in Rotating Disks Using Fidelity LES - Mercedes Benz

      • Adhi Venugopalan V, Mercedes Benz
      • Pradeep Nagabhushan, Mercedes Benz
      • Harsha Suresh, Mercedes Benz

      Best Poster Winners

      • Precise Latency Landing on Specific Sinks - Intel

      • Roopa Tigad, Intel

      • Multi-Core SoC Verification Made Easy with Portable Stimulus - Analog Devices

      • Vivek Gopalkrishna, Analog Devices
      • Ponnambalam Lakshmanan, Analog Devices
      • Nitish Swamy, Analog Devices
      • Maheshwaran B, Cadence