September 12, 2024
CUSTOM AND ANALOG DESIGN: IMPLEMENTATION
- Automatic Layout Migration (ALM) Across Advanced Process Nodes to Enhance Productivity - Marvell
- Layout Implementation for Advanced Tech Nodes Using Virtuoso Enhanced Features - Qualcomm
CUSTOM AND ANALOG DESIGN: VERIFICATION
- Leveraging Virtuoso ADE Explorer for Efficient Circuit Verification: A Focus on 2D Shmoo Plots - Rambus
- Next-Gen SV Netlister Using VSVN Flow - Analog Devices
DIGITAL DESIGN ADVANCEMENT WITH AI
- Maximizing Cumulative PPA Gain with Cadence Cerebrus ML-Driven Model - Analog Devices
DIGITAL DESIGN AND IMPLEMENTATION
- Techniques to Achieve Optimum PPA in PNR Using Innovus - Infineon
- Precise Latency Landing on Specific Sinks - Intel
DIGITAL SIGNOFF
- Enabling Efficient Statistical EM Budgeting in ASIC RV Tools - Intel
September 13, 2024
ADVANCED VERIFICATION METHODOLOGY
- Making Efficient Verification Environment Through Cadence ML Solutions - Rambus
- Comprehensive Verification of PCIe Using NDie Approach - Samsung
- Real Number Modelling in NAND Flash Memory Verification - Western Digital
PERFORMANCE AND SMART BUG HUNTING
- Coverage Automation to Accelerate Coverage Closure for SoCs - Texas Instruments
- AssertPlus: Comprehensive Plug n Play Assertion/Checkers Library for Efficient Verification - Google
- Automatic Multiple Snapshot Incremental Elaboration(AUTO MSIE) – A Novel Approach in Xcelium Snapshot Generations - Analog Devices
HARDWARE AND SYSTEM VERIFICATION
- UPF Integrated Power-Aware Emulation: An Accelerated Methodology for Low-Power Design Verification - Samsung
- Multi-Core SoC Verification Made Easy with Portable Stimulus - Analog Devices
PCB AND SYSTEM DESIGN AND ANALYSIS
- Bridging the Gap Between Test Characterization Board and System Level Board using Cadence SI/PI Solvers - Qualcomm
- Designing for Reality Using Allegro X 23.1 - Infineon
